The present invention relates to a data processing apparatus for processing bit map data, a method for processing the bit map data in this data processing apparatus, and a graphic processor for constituting this processing method, and also a graphic processing system.
In conventional data processing apparatuses, the following two methods have been employed when bit map data stored into a main memory is processed. According to one method, a central processing unit directly accesses the main memory so as to update the bit map data. In accordance with the other method, a graphic processor exclusively used for processing the bit map data is prepared, and the main memory is accessed by this graphic processor in order to update the bit map data, as described in the pending patent application Ser. No. 905, 173 entitled "GRAPHIC PROCESSING SYSTEM", filed by K. Katsura et al. on Sep. 9, 1986, the disclosure of which is incorporated herein by reference.
In the first-mentioned method, if the address space of the main memory has not yet been made virtual or virtually processed, the central processing unit calculates the physical address of the data to be processed and accesses this data. To the contrary, if the address space of the main memory has been virtually processed, the virtual address of the data to be processed is first calculated by the memory management unit employed by the central processing unit, and the main memory is accessed after this virtual address is translated into the physical address. At this time, if no data to be processed is present in the main memory, the central processing unit accesses this data after the necessary data has been read out from the secondary storage unit and supplied to the main memory.
On the other hand, in the latter-mentioned method, the graphic processor accesses the main memory in accordance with the instruction from the central processing unit. At this time, only typical points of the data to be processed are designated by the physical information of the main memory. In other words, existence of the respective data to be processed has been calculated by employing the internal calculating circuit by the graphic processor based upon the information on the given typical points. Since the address information of the typical points given to the graphic processor correspond to the physical address, the address information on the respective data to be processed, which is calculated by the graphic processor, similarly corresponds to the physical address, so that the graphic processor can directly access the main memory without using the central processing unit. At this time, if the address space of the main memory has not yet been virtually processed, no specific care is required. To the contrary, if the address space of the main memory has been virtually processed, the central processing unit must instruct the graphic processor to perform the drawing operation in a unit of the address space continued on the main memory. Also, when the main memory is under accessing operation by the graphic processor, care must be taken such that the data to be processed continuously exists on the main memory.
In one Japanese patent publication JP-A-62-62390, there is disclosed the graphic processor for drawing characters on the bit map. Another Japanese patent publication JP-A-63-91789 discloses the graphic processor for transferring the bit map data between the main memory and frame buffer in order to display the multiwindow.
There is a problem that a lengthy data processing time is required for the bit map data when the central processing unit solely accesses the main memory. To achieve highspeed data processing, the graphic processors which are exclusively used for processing the bit map data have been invented. However, no specific care has been taken for such a case that the main memory is virtually formed in the conventional graphic processors. As previously described, the drawing instruction must be given in a unit of address space continued on the main memory for these graphic processors. Moreover, further care must be taken that the data to be processed is continuously present in the main memory under the accessing operation to the main memory by the graphic processors. To perform the above-described processings, the workload of the drawing process given to the central processing unit cannot be sufficiently reduced, which may cause the overall performance of the data processor to be lowered. There have been proposed two methods for using the system bus. That is to say, in accordance with the first method, when the data transfer unit such as the direct memory access controlling unit performs the data transfer operation with the main memory for storing therein the processed data by employing the system bus, once the data transfer operation is commenced, the system bus is continuously occupied until this data transfer operation is completed (i.e., burst transfer method). In accordance with the second method, the occupation rate of the system bus is previously set, and both the central processing unit and data transfer unit alternately use the system bus (i.e., cycle steal method.)
In the burst transfer method, there is a small software overhead to arbitrate the system bus and also the higher data transfer efficiency can be expected, as compared with the cycle steal method. However, there is a problem that the central processing unit cannot execute the process until the processing operation by the data transfer unit is accomplished in case that the central processing until requires performance of the urgent processing operation during the data transfer operation by the data transfer unit due to external reasons and internal reasons of the system. There are further problems that the construction of the bus arbitrator becomes complex and also that a cumbersome procedure is required to restart the system after the data transfer operation by the data transfer unit is interrupted, and the central processing unit occupies the system bus so as to perform the process corresponding to the interruption.
On the other hand, in the cycle steal method, the central processing unit can temporarily execute the process of the data transfer operation. However, there is such a problem that the software overhead for acquiring the system bus by the central processing unit becomes large, the data transfer efficiency is lowered, and also a lengthy processing time is required, as compared with the burst transfer method. These problems may be similarly applied to such a data transfer operation between a main memory and frame buffer, and also to a drawing processing operation by a main memory under a condition that a data transfer unit is substituted by a graphic processor.